Synopsys IC Compiler II vP-2019.03

Synopsys IC Compiler is the industry-leading place and route solution that delivers the best quality of results (QoR) for next-generation designs across all market verticals and process technologies while providing unprecedented productivity.

IC Compiler II includes innovations for flat and hierarchical design planning, early design exploration, density-aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signal closure. IC Compiler II is specifically designed to address the aggressive performance, power, area (PPA), and time-to-market pressures of leading designs.

Key technologies include a pervasive parallel optimization framework, multi-objective global placement, routing-based location optimization, full-flow-based simultaneous clock and data optimization, total power optimization, FinFET-aware flow optimization, and machine learning (ML) for fast and predictive design closure.

Advanced Fusion technologies deliver IR drop-based optimization, PrimeTime delay calculation in IC Compiler II, comprehensive path-based analysis (PBA), and ECO signoff in location and path for unparalleled QoR and design convergence.

Features and functions of the Synopsys IC Compiler program:

• Hierarchical infrastructure: Enables massive parallelism, scalable data access, and efficient modification of large designs.
• Multi-corner, multi-mode (MCMM) architecture: Supports analysis and optimization across multiple modes and corners.
  Next-generation design planning: Combines novel, adaptive-abstract, and parallel computing techniques for efficient planning and exploration.
• Global optimization: Enables optimization of large pieces of logic simultaneously, reducing the risk of local minima and improving design quality.
• Clock Synthesis: Supports advanced clock synthesis and optimization, including simultaneous clock and data (CCD) optimization.
• Physical synthesis and optimization: Includes techniques for density-aware placement, pin allocation, and optimization, as well as support for complex design styles and flows.
• Timing Engine: Designed for modern designs with multiple modes and corners, featuring a superb cross-flow execution timer