Silvaco Analog Custom IC Design is a unified, end-to-end electronic design automation (EDA) platform for designing analog, RF, mixed-signal, and custom digital integrated circuits. Unlike point tools that handle only simulation or layout, Silvaco’s platform provides a tightly integrated flow from schematic capture and circuit simulation through physical layout, parasitic extraction, and verification to final tapeout. It is known for its high performance, deep foundry support (including advanced FinFET nodes), and competitive positioning as an alternative to Cadence Virtuoso/Spectre and Synopsys Custom Compiler.
Schematic Editor (Gateway): Hierarchical schematic capture with advanced connectivity-driven design (CDD) and integrated design rule checking (DRC).
Circuit Simulation (SmartSpice): Industry-standard, high-performance SPICE simulator with:
Advanced Analysis: Transient, AC, DC, noise, stability, Monte Carlo, and worst-case analysis.
RF & High-Speed Features: Harmonic balance, shooting Newton, periodic AC analysis.
AI/ML Accelerated Simulation: SmartSpice AI for predicting simulation results and reducing runtime.
Waveform Viewer (T3Ster): Advanced waveform analysis, measurement, and post-processing with scripting (TCL, Python).
Layout Editor (Expert): High-performance, full-featured layout editor supporting:
Advanced Node Support: FinFET, FD-SOI, and planar nodes down to 3nm.
Parameterized Cells (PCells) and auto-routing for analog structures.
Real-time DRC and layout-vs-schematic (LVS) during editing.
Parasitic Extraction (Raphael, Melete): 3D field solver (Raphael) for critical nets and fast RC extractor (Melete) for full-chip.
Physical Verification (Clever): Sign-off quality DRC, LVS, and parasitic extraction (PEX) with support for foundry decks (Calibre, ICV compatible).
EM Analysis (VeloceRF): Integrated 3D planar electromagnetic solver for inductors, transformers, and transmission lines.
Reliability Analysis (Guardian): Simulate aging effects (HCI, BTI, TDDB) and electromigration (EM/IR) across corners.
Yield Analysis (Variation Designer): Statistical analysis for process variation and design-centering.
The 2024 update focuses on AI-driven design, advanced node support, and cloud scalability:
AI-Powered Design Assistant (AIDA): New context-aware AI engine that suggests circuit topologies, sizing recommendations, and layout patterns based on specifications and past successful designs.
3nm & Sub-3nm PDK Support: Enhanced support for GAA (Gate-All-Around) nanosheet and CFET technologies with updated design rules, PCells, and simulation models in the platform.
Cloud-Native Design Flow: Full support for cloud-based execution (AWS, Google Cloud, Azure). Designers can launch simulation jobs and batch runs directly to cloud instances from the desktop environment with automated resource scaling.
Enhanced Mixed-Signal Verification: Tighter integration with Silvaco’s Symphony for mixed-signal simulation, enabling easier co-simulation of analog blocks with complex digital controllers (e.g., UVM-based testbenches).
Real-Time Collaboration Features: Multi-user design editing with live change propagation and commenting, improving teamwork for remote and global design teams.
Performance & Capacity: Up to 2x faster layout editing performance for large, hierarchical blocks and improved memory management for >100M instance designs.
OS: Red Hat Enterprise Linux 8.6, Rocky Linux 8.8, AlmaLinux 8.8
CPU: Intel Xeon E-2388G or AMD Ryzen 9 5900X (8 cores / 16 threads)
RAM: 64 GB
GPU: Professional GPU (NVIDIA RTX A2000, 6GB VRAM) with certified drivers for smooth layout display
Storage: 500 GB NVMe SSD (PCIe 3.0+) for OS, software, and active projects
Network: 1 GbE for license/server access; Low latency to NFS/SAN for shared PDK/data
OS: RHEL 9.2, Rocky Linux 9.2 (with latest kernel and patches)
CPU: Dual AMD EPYC 9554 (64 cores each) or Intel Xeon Platinum 8468 (48 cores each) for massive parallel simulation (Monte Carlo, corners). High single-thread speed also critical for interactive tasks.
RAM: 256 GB – 1 TB (Layout and simulation of large analog arrays or full SerDes blocks are memory intensive)
GPU: NVIDIA RTX A5500 (24GB VRAM) or A6000 (48GB VRAM) for complex layout visualization and GPU-accelerated simulation post-processing.
Storage: Tiered Setup is critical:
Local Scratch: 2 TB NVMe SSD (PCIe 4.0) for simulation temp files.
Shared Project Data: 10+ TB high-performance parallel file system (Lustre, WEKA, GPFS) or all-flash NAS for PDK, libraries, and design databases.
Network: 10 GbE minimum; 25/40/100 GbE for data-intensive environments. InfiniBand for HPC cluster access.
License Server: A dedicated, reliable server for FlexNet license daemon.
Price: 325 $
Price Currency: $
Operating System: Windows
Application Category: Electronics
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