Active-HDL is a Windows based software for building, designing and simulating field programmable gate arrays ( FPGA ) in team environments. The integrated Active-HDL design environment provides a complete set of graphical design and multilingual simulation tools (with right-to-left support) for rapid development, review and modification of FPGA designs.

Design flow management in software invokes more than 120 tools for creating electronic design automation (EDA) and FPGAs at the time of design entry, simulation, synthesis, and implementation flows, allowing the team to control the entire development process. FPGA, remain on a common platform. Active-HDL supports all industry leading FPGA devices including Altera, Atmel, Lattice, Microsemi, Quicklogic and Xilinx.

Features of Active-HDL software:

• Team and Unified Design Management: Maintaining consistency across local or remote teams
• Configurable EDA/FPGA flow management: Interoperate with over 120 vendor tools to keep teams on a common platform
• Quickly expand designs with texts, diagrams and state devices
• Distribute or provide IPs more securely and reliably with consistent and standardized encryption
• A powerful and multilingual shared kernel simulator with support for VHDL, Verilog, SystemVerilog and SystemC
• Ensure code quality and validity using interactive graphical debugging and code quality tools