Mentor Questa Formal, the software from Siemens EDA, part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. In addition to the large design size, inclusion of multiple embedded processors and advanced interconnect systems, the increased software content and configurability required by multi-platform designs require a functional verification solution that unifies a broad arsenal of verification solutions.

Questa lets you leverage CDC verification, formal verification, mixed-signal verification, portable actuators and other powerful technologies to maximize the effectiveness of your verification at the block and subsystem level so that your system-level verification can focus on system-level functionality including software, without having to worry about low-level bugs that kill your productivity. No one wants to compromise product quality.

However, time-to-market pressures dominate SoC projects. Delivering quality in the application requires improving time to meet coverage and quality goals and improving productivity. Questa Formal statically analyzes the behavior of a design with respect to a given set of features, then exhaustively examines all possible input sequences in a breadth-first search manner. This reveals design errors that would otherwise be missed or impractical to find with simulation-based methods.

Features and functions of the Mentor Questa Formal program:

• Advanced Coating Solutions
• Extensive analysis of clock domain busses present in designs.
• Checking static and conditional binding
• Checking the integrity of the secure path
• Identifying inaccessible code
• X-mode release
• State space analysis and registration verification
• Sequential logical equivalence